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rom P r o d u c t IIn n o vva t i o n FF r o m nn SA03o a
SA03 SA03
Pulse Width Modulation Amplifier
FEATURES
* WIDESUPPLYRANGE--16-100V * 30ACONTINUOUSTO60Ccase * 3PROTECTIONCIRCUITS * ANALOGORDIGITALINPUTS * SYNCHRONIZEDOREXTERNALOSCILLATOR * FLEXIBLEFREQUENCYCONTROL
SA03
USA TE9493 11
BeO
APPLICATIONS
* MOTORSTO4HP *REACTIVELOADS * LOWFREQUENCYSONAR * LARGEPIEZOELEMENTS * OFF-LINEDRIVERS * C-DWELDCONTROLLER
EXTERNALCONNECTIONS
12-PINPOWERDIP PACKAGESTYLECR
DESCRIPTION
The SA03 is a pulse width amplifier that can supply 3000W to the load. An internal 45kHz oscillator requires no external components. The clock input stage divides the oscillator frequency by two, which provides the basic switching of 22.5 kHz. External oscillators may also be used to lower the switching frequency or to synchronize multiple amplifiers. Current sensing is provided for each half of the bridge giving amplitude and direction data. A shutdown input turns off all four drivers of the H bridge output.A high side current limit and the programmable low side current limit protect the amplifier from shorts to supply or ground in addition to load shorts. The H bridge output MOSFETs are protected from thermal overloads by directly sensing the temperature of the die.The 12-pin hermetic MO-127 power package occupies only 3 square inches of board space.
CLK IN CLK OUT +PWM -PWM/RAMP GND ILIM/SHDN
1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7
ISENSE A A OUT * VCC * +VS B OUT I SENSE B
Case tied to pin 5. Allow no current in case. Bypassing of supplies is required. Package is Apex MO-127 (STD). See Outline Dimensions/Packages in Apex data book. If +PWM > RAMP/-PWM then A OUT > B OUT. * See text.
BLOCKDIAGRAMANDTYPICALAPPLICATION
Vcc 10 +PWM 3 4 -PWM/RAMP 470pF 56K
CURRENT LIMIT PWM
9 +VS
B OUT OUTPUT DRIVERS 8 11 A OUT 1K SHUTDOWN CONTROL I SENSE A 12 6 ILIM/SHDN 7 I SENSE B RSENSE 5K .01F MOTOR
CLK OUT 2 OSC /2
CLK IN 1 5 CONTROL SIGNAL GND
RSENSE 1K
5V
5V
SA03U
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2009 (All Rights Reserved)
MAY 2009 1 APEX - SA03UREVH
SA03
ABSOLUTEMAXIMUMRATINGS
P r o d u c t I n n o v a t i o nF r o m
SPECIFICATIONS
PARAMETER CLOCK (CLK) CLK OUT, high level4 CLK OUT, low level4 FREQUENCY RAMP, center voltage RAMP, P-P voltage CLK IN, low level4 CLK IN, high level4 OUTPUT TOTAL RON EFFICIENCY, 10A output SWITCHING FREQUENCY CURRENT, continuous4 CURRENT, peak4 POWER SUPPLY VOLTAGE, VS VOLTAGE, VCC CURRENT, VCC CURRENT, VCC, shutdown CURRENT, VS ILIM/SHUTDOWN TRIP POINT INPUT CURRENT THERMAL3 RESISTANCE, junction to case RESISTANCE, junction to air TEMPERATURE RANGE, case
SUPPLY VOLTAGE, +VS SUPPLY VOLTAGE, VCC POWER DISSIPATION, internal TEMPERATURE, pin solder - 10s TEMPERATURE, junction2 TEMPERATURE, storage OPERATING TEMPERATURE RANGE, case INPUT VOLTAGE, +PWM INPUT VOLTAGE, -PWM INPUT VOLTAGE, ILIM TEST CONDITIONS2 MIN TYP
100V 16V 300W 300C 150C -65 to +150C -55 to +125C 0 to +11V 0 to +11V 0 to +10V MAX UNITS
IOUT 1mA IOUT 1mA
4.8 0 44 0 3.7
45 5 4
5.3 .4 46 .9 5.4
V V kHz V V V V
.16 VS = 100V OSC in / 2 60C case 22 30 40 97 22.5 23
% kHz A A
Full temperature range Full temperature range IOUT = 0 No Load
165 14
60 15
100 16 80 50 50
V V mA mA mA
90
110 100
mV nA
Full temperature range, for each die Full temperature range Meets full range specifications
.83 12 -25 +85
C/W C/W C
NOTES: 1. 2. 3. 4. 5.
Each of the two active output transistors can dissipate 150W. Unless otherwise noted: TC = 25C, VS, VCC at typical specification. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet. Guaranteed but not tested. If 100% duty cycle is not required VS(MIN) = 0V. The SA03 is constructed from MOSFET transistors. ESD handling procedures must be observed. The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to temperatures in excess of 850C to avoid generating toxic fumes.
CAUTION
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SA03U
P r o d u c t I n n o v a t i o nF r o m
SA03
CLOCK LOADING CLOCK FREQUENCY OVER TEMP
102.0
NORMALIZED FREQUENCY, (%)
POWER DERATING
INTERNAL POWER DISSIPATION, (W)
150
NORMALIZED FREQUENCY, (%)
100 99 98
125 100 75 50 25 0 EACH ACTIVE OUTPUT TRANSISTOR 0 50 75 100 25 CASE TEMPERATURE, (C) 125
101.5 101.0 100.5 100 99.5 99.0 98.5 98.0 25 50 75 100 125 -50 -25 0 CASE TEMPERATURE, (C)
97 96 95 F NOMINAL = 45kHz 10K 100K 1M CLOCK LOAD RESISTANCE, ()
3
FLYBACK CURRENT, Isd (A)
REVERSE DIODE
10
TOTAL VOLTAGE DROP, (V)
TOTAL VOLTAGE DROP
CASE TEMPERATURE 60C 85C 100C 125C
2 10 9 7 6 5 4 3 2 1 8 7 6 5 0.8 1.0 1.2 1.4 1.6 0.6 SOURCE TO DRAIN DIODE VOLTAGE 8 6 4 2 0 0
-55C 5
-25C
25C 30
NORMALIZED Vcc QUIESCENT CURRENT, (%)
10 15 20 25 OUTPUT CURRENT, (A)
30 28
CONTINUOUS AMPS
CONTINUOUS OUTPUT
100
DUTY CYCLE VS ANALOG INPUT
B OUT
100 95 90 85 80 75
Vcc QUIESCENT CURRENT
80
DUTY CYCLE, (%)
26 24 22 20 18 16 25 50 75 100 125 CASE TEMPERATURE, (C) 150
60 40 20 A OUT 0 3 4 5 6 ANALOG INPUT, (V) 7
5
10 15 20 25 SWITCHING FREQUENCY, F (kHz)
NORMALIZED Vcc QUIESCENT CURRENT, (%)
NORMALIZED Vs QUIESCENT CURRENT, (%)
115 110 105 100 95 90 85 80
180 160 140 120 100 80 60 40 20 0
NORMALIZED Vs QUIESCENT CURRENT, (%)
Vcc QUIESCENT CURRENT
Vcc = 15V F = 22.5 kHz NORMAL OPERATION
Vs QUIESCENT VS VOLTAGE
100
Vs QUIESCENT VS FREQUENCY
Vs = 60V, NO LOAD
90 80 70 60 50 40
-55C 125C
SHUTDOWN OPERATION -50 -25 0 25 50 75 100 125 CASE TEMPERATURE, (C)
20
40 60 Vs, (V)
80
100
5
10 15 20 25 SWITCHING FREQUENCY, F (kHz)
SA03U
3
SA03
GENERAL
P r o d u c t I n n o v a t i o nF r o m
Please read Application Note 30 on "PWM Basics". Refer to Application Note 1 "General Operating Considerations" for helpful information regarding power supplies, heat sinking and mounting. Visit www.Cirrus.com for design tools that help automate pwm filter design; heat sink selection; Apex Precision Power's complete Application Notes library; Technical Seminar Workbook; and Evaluation Kits.
CLOCKCIRCUITANDRAMPGENERATOR
The clock frequency is internally set to a frequency of approximately 45kHz. The CLK OUT pin will normally be tied to the CLK IN pin. The clock is divided by two and applied to an RC network which produces a ramp signal at the -PWM/ RAMP pin. An external clock signal can be applied to the CLK IN pin for synchronization purposes. If a clock frequency lower than 45kHz is chosen an external capacitor must be tied to the -PWM/RAMP pin. This capacitor, which parallels an internal capacitor, must be selected so that the ramp oscillates 4 volts p-p with the lower peak 3 volts above ground.
PWMINPUTS
The full bridge driver may be accessed via the pwm input comparator. When +PWM > -PWM then A OUT > B OUT. A motion control processor which generates the pwm signal can drive these pins with signals referenced to GND.
PROTECTIONCIRCUITS
In addition to the externally programmable current limit there is also a fixed internal current limit which senses only the high side current. It is nominally set to 140% of the continuous rated output current. Should either of the outputs be shorted to ground the high side current limit will latch off the output transistors. Also, the temperature of the output transistors is continually monitored. Should a fault condition occur which raises the temperature of the output transistors to 165C the thermal protection circuit will activate and also latch off the output transistors. In either case, it will be necessary to remove the fault condition and recycle power to VCC to restart the circuit.
noise spikes could trip the current limit threshold which is only 100 mV. RFILTER and CFILTER should R LIMIT be adjusted so as to reduce the I SENSE B switching noise well below 100 1K mV to prevent false current limiting. The sum of the DC level plus R LIMIT the noise peak will determine the current limitSHUTDOWN I LIMIT/SHDN R ing value. As in SIGNAL FILTER most switching R SHDN C FILTER circuits it may be difficult to deFIGURE B. CURRENT LIMIT WITH termine the true SHUTDOWN CURRENT MODE. noise amplitude without careful attention to grounding of the oscilloscope probe. Use the shortest possible ground lead for the probe and connect exactly at the GND terminal of the amplifier. Suggested starting values are CFILTER = .01uF, RFILTER = 5k . The required value of RLIMIT in voltage mode may be calculated by: RLIMIT = .1 V / ILIMIT where RLIMIT is the required resistor value, and ILIMIT is the maximum desired current. In current mode the required value of each RLIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If RSHDN is used it will further divide down the sense voltage. The shutdown divider network will also have an effect on the filtering circuit.
I SENSE A 1K
BYPASSING
Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and low efficiency operation as well as excessive ringing at the outputs. The Vs supply should be bypassed with at least a 1F ceramic capacitor in parallel with another low ESR capacitor of at least 10F per amp of output current. Capacitor types rated for switching applications are the only types that should be considered. The bypass capacitors must be physically connected directly to the power supply pins. Even one inch of lead length will cause excessive ringing at the outputs. This is due to the very fast switching times and the inductance of the lead connection. The bypassing requirements of the Vcc supply are less stringent, but still necessary. A .1F to .47F ceramic capacitor connected directly to the Vcc pin will suffice.
CURRENTLIMIT
There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted in the voltage mode connection but both must be used in the current mode connection (see figures A and B). It is recommended that RLIMIT resistors be non-inductive. Load current flows in the I SENSE pins. To avoid errors due to lead lengths connect the I LIMIT/SHDN pin directly to the RLIMIT resistors (through I SENSE A the filter network and shutdown diR LIMIT vider resistor) and I SENSE B connect the RLIMIT 1K SHUTDOWN resistors directly to I LIMIT/SHDN R SIGNAL FILTER the GND pin. Switching noise R SHDN C FILTER spikes will invariably be found at the I FIGURE A. CURRENT LIMIT WITH SENSE pins. The SHUTDOWN VOLTAGE MODE.
STARTUPCONDITIONS
The high side of the all N channel output bridge circuit is driven by bootstrap circuit and charge pump arrangement. In order for the circuit to produce a 100% duty cycle indefinitely the low side of each half bridge circuit must have previously been in the ON condition. This means, in turn, that if the input signal to the SA03 at startup is demanding a 100% duty cycle, the output may not follow the command and may be in a tristate condition. The ramp signal must cross the input signal at some point to correctly determine the output state. After the ramp crosses the input signal level one time, the output state will be correct thereafter.
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SA03U
P r o d u c t I n n o v a t i o nF r o m
SA03
ContACting CiRRUS LogiC SUPPoRt
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com
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SA03U
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